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cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av 3.3v 4k/8k/16k x 16/18 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06052 rev. *m revised march 30, 2011 features true dual-ported memory cells which enable simultaneous access of the same memory location 4, 8 or 16k 16 organization (cy7c024av/024bv [1] / 025av/026av) 4 or 8k 18 organization (cy7c0241av/0251av) 16k 18 organization (cy7c036av) 0.35 micron cmos for optimum speed and power high speed access: 20 and 25 ns low operating power ? active: i cc = 115 ma (typical) ? standby: i sb3 = 10 ? a (typical) fully asynchronous operation automatic power down expandable data bus to 32 bits, 36 bits or more using master and slave chip select when using more than one device on chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to- port communication separate upper byte and lower byte control pin select for master or slave (m/s) commercial and industrial temperature ranges available in 100-pin pb-free tqfp and 100-pin tqfp notes 1. cy7c024av and cy7c024bv are functionally identical. 2. io 8 ?io 15 for x16 devices; io 9 ?io 17 for x18 devices. 3. io 0 ?io 7 for x16 devices; io 0 ?io 8 for x18 devices. 4. a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices. 5. busy is an output in master mode and an input in slave mode. r/w l oe l io 8/9l ?io 15/17l io control address decode a 0l ?a 11/12/13l ce l oe l r/w l busy l io control ce l interrupt semaphore arbitration sem l int l m/s ub l lb l io 0l ?io 7/8l r/w r oe r io 8/9l ?io 15/17r ce r ub r lb r io 0l ?io 7/8r ub l lb l a 0l ?a 11/1213l true dual-ported ram array a 0r ?a 11/12/13r ce r oe r r/w r busy r sem r int r ub r lb r address decode a 0r ?a 11/12/13r [2] [2] [3] [3] [5] [5] 12/13/14 8/9 8/9 12/13/14 8/9 8/9 12/13/14 12/13/14 [4] [4] [4] [4] logic block diagram [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 2 of 20 pin configurations figure 1. 100-pin tqfp (top view) notes 6. a 12l on the cy7c025av. 7. a 12r on the cy7c025av. 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc nc nc io 10l io 11l io 15l v cc gnd io 1r io 2r v cc 90 91 a 3l m/s busy r io 14l gnd io 12l io 13l a 1r a 2r a 3r a 4r nc nc nc nc io 3r io 4r io 5r io 6r nc nc nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 io 9l io 8l io 7l io 6l io 5l io 4l io 3l io 2l gnd io 1l io 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l io 0r io 7r io 8r io 9r io 10r io 11r io 12r io 13r io 14r gnd io 15r ? r r\w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c024av/024bv (4k 16) r/ w l [6] [7] cy7c025av (8k 16) [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 3 of 20 figure 2. 100-pin tqfp (top view) notes 8. a 12l on the CY7C0251AV. 9. a 12r on the CY7C0251AVc. pin configurations (continued) 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc io 11l io 12l io 16l v cc gnd io 1r io 2r v cc 90 91 a 3l m/ s busy r io 15l gnd io 13l io 14l a 1r a 2r a 3r a 4r nc nc nc nc io 3r io 4r io 5r io 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 io 9l io 7l io 6l io 5l io 4l io 3l io 2l io 10l gnd io 1l io 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l io 0r io 7r io 16r io 9r io 10r io 11r io 12r io 13r io 14r gnd io 15r oe r r/ w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c0241av (4k 18) io 8l io 17l io 8r io 17r r/ w l [9] [8] 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc nc a6l a5l a4l int l a2l a0l gnd m/ s a0r a1r a1l a3l busy r int r a2r a3r a4r a5r nc nc nc busy l 58 57 56 55 54 53 52 51 cy7c026av (16k 16) nc nc nc nc io10l io11l io15l io13l io14l gnd io0r vcc io3r gnd io12l io1r io2r io4r io5r io6r nc nc nc nc vcc 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 io9l io8l io7l io6l io5l io4l io0l io2l io1l vcc r/ w l ub l lb l gnd io3l sem l ce l a13l a12l a11l a10l a9l a8l a7l oe l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 a6r a7r a8r a9r a10r a11r ce r a13r ub r gnd r/ w r gnd io14r lb r a12r oe r io15r io13r io12r io11r io10r io9r io8r io7r sem r 33 32 31 30 29 28 27 26 CY7C0251AV (8k 18) [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 4 of 20 figure 3. 100-pin tqfp (top view) pin configurations (continued) 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc io 11l io 12l io 16l v cc gnd io 1r io 2r v cc 90 91 a 3l m/s busy r io 15l gnd io 13l io 14l a 1r a 2r a 3r a 4r nc nc nc io 3r io 4r io 5r io 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 io 9l io 7l io 6l io 5l io 4l io 3l io 2l io 10l gnd io 1l io 0l oe l sem l v cc ce l ub l lb l a 11l a 10l a 9l a 8l a 7l a 6l io 0r io 7r io 16r io 9r io 10r io 11r io 12r io 13r io 14r gnd io 15r oe r r/w r gnd sem r ce r ub r lb r a 11r a 10r a 9r a 8r a 7r a 6r a 5r io 8l io 17l io 8r io 17r r/w l cy7c036av (16k 18) a 13l a 13r a 12l a 12r selection guide parameter cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av -20 cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av -25 unit maximum access time 20 25 ns typical operating current 120 115 ma typical standby current for i sb1 (both ports ttl level) 35 30 ma typical standby current for i sb3 (both ports cmos level) 10 10 ? a [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 5 of 20 architecture the cy7c024av/024bv/025av/026av and cy7c0241av/0251av/036av consist of an array of 4k, 8k, and 16k words of 16 and 18 bits each of dual-port ram cells, io and address lines, and control signals (ce , oe , rw ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes and reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port to port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can func tion as a master (busy pins are outputs) or as a slave (busy pins are inputs). they also have an automatic power down feature controlled by ce . each port has its own output enable control (oe ), which enables data to be read from the device. functional description the cy7c024av/024bv/025av/026av and cy7c0241av/0251av/036av are low power cmos 4k, 8k, and 16k 16/18 dual port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. there are two ports permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be used as standalone 16 or18-bit dual port static rams or multiple devices can be combined to function as a 32 or 36-bit or wider master and slave dual port static ram. an m/s pin is provided for implementing 32 or 36-bit or wider memory applications. it does not need separate master and slave devices or additional discrete logic. application areas include interprocessor/mul tiprocessor designs, communica- tions status buffering, and dual port video and graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic has eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c024av/024bv/025av/026av and cy7c0241av0251av/036av are avail able in 100-pin pb-free thin quad flat pack (tqfp) and 100-pin tqfp. write operation data must be set up for a duration of t sd before the rising edge of rw to guarantee a valid write. a write operation is controlled by either the rw pin (see figure 8 on page 12) or the ce pin (see figure 9 on page 12). required inputs for non-contention opera- tions are summarized in ta b l e 1 on page 7. if a location is being written to by one port and the opposite port tries to read that location, there must be a port to port flowthrough delay before the data is read on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the us er must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user wants to access a semaphore flag, then the sem pin and oe must be asserted. interrupts the upper two memory locations are for message passing. the highest memory location (fff for the cy7c024av/024bv/41av/1fff for the cy7c025av/51av, pin definitions left port right port description ce l ce r chip enable r/w l r/w r read and write enable oe l oe r output enable a 0l ?a 13l a 0r ?a 13r address (a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k) io 0l ?io 17l io 0r ?io 17r data bus input and output sem l sem r semaphore enable ub l ub r upper byte select (io 8 ?io 15 for x16 devices; io 9 ?io 17 for x18 devices) lb l lb r lower byte select (io 0 ?io 7 for x16 devices; io 0 ?io 8 for x18 devices) int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 6 of 20 3fff for the cy7c026av/36av) is the mailbox for the right port and the second highest memory location (ffe for the cy7c024av/024bv/41av/1ffe for the cy7c025av/51av, 3ffe for the cy7c026av/36av) is the mailbox for the left port. when one port writes to the ot her port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts a nd their interaction with busy are summarized in table 2 on page 7 . busy the cy7c024av/024bv/025av/026av and cy7c0241av/0251av/036av provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains per mission to the location, but it is not predictable which port gets that permission. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin helps to expand the word width by configuring the device as a master or a slave. the busy output of the master is connected to the busy input of the slave. this enables the device to interface to a master device with no external compo- nents. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ). otherwise, the slave chip may begin a write cycle during a contention situat ion. when tied high, the m/s pin enables the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c024av/024bv/025av/026av and cy7c0241av/0251av/036av provide eight semaphore latches, which are separate from the dual port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifi es its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource. otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the sema phore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and rw are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only io 0 is used. if a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 on page 7 shows sample semaphore operations. when reading a semaphore, all 16 and 18 data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one of them. but th ere is no guarantee which side controls the semaphore. [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 7 of 20 table 1. non-contending read/write inputs outputs operation ce r/w oe ub lb sem io 9 ? io 17 io 0 ? io 8 h x x x x h high z high z deselected: power down x x x h h h high z high z deselected: power down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) [10] left port right port function r/w l ce l oe l a 0 l ?13 l int l r/w r ce r oe r a 0r?13r int r set right int r flag l l x fff [13] xxxx x l [12] reset right int r flag x x x x x x l l fff (or 1/3fff) h [11] set left int l flag xxx x l [11] l l x 1ffe (or 1/3ffe) x reset left int l flag x l l 1ffe [13] h [12] xxx x x table 3. semaphore operation example function io 0 ? io 17 left io 0 ? io 17 right status no action 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore-free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore-free notes 10. see functional description on page 5 for specific highes t memory locations by device. 11. if busy r =l, then no change. 12. if busy l =l, then no change. 13. see functional description on page 5 for specific addresses by device. [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 8 of 20 maximum ratings exceeding maximum ratings [14] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied ......................... ................... ?55c to +125c supply voltage to ground potential............... ?0.5v to +4.6v dc voltage applied to outputs in high-z state ......................... ?0.5v to v cc + 0.5v dc input voltage [15] ............................... ?0.5v to v cc + 0.5v output current into outputs (low) ............................. 20 ma static discharge voltage.......................................... > 2001v latch-up current.................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v ? 300 mv industrial [16] ?40c to +85c 3.3v ? 300 mv electrical characteristics over the operating range parameter description cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av unit -20 -25 min typ max min typ max v oh output high voltage (v cc =3.3v) 2.4 2.4 v v ol output low voltage 0.4 0.4 v v ih input high voltage 2.0 2.0 v v il input low voltage ?0.3 [17] 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 ? a i ix input leakage current ?10 10 ?10 10 ? a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com?l. 120 175 115 165 ma ind. [16] 135 185 ma i sb1 standby current (both ports ttl level) ce l & ce r ? v ih , f = f max com?l. 35 45 30 40 ma ind. [16] 40 50 ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max com?l. 75 110 65 95 ma ind. [16] 75 105 ma i sb3 standby current (both ports cmos level) ce l & ce r ? v cc ? 0.2v, f = 0 com?l. 10 500 10 500 ? a ind. [16] 10 500 ? a i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max [18] com?l. 70 95 60 80 ma ind. [16] 70 90 ma capacitance parameter [19] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf notes 14. the voltage on any input or io pin cannot exceed the power pin during power up. 15. pulse width < 20 ns. 16. industrial parts are available in cy7c026av and cy7c036av only. 17. vil > ?1.5v for pulse width less than 10ns. 18. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 19. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 9 of 20 figure 4. ac test loads and waveforms 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3v output r2 = 435 ? c= 30 pf v th =1.4v output c= 30pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3v output c= 5pf r th = 250 ? ? ? including scope and jig) (used for t lz , t hz , t hzwe , and t lzwe switching characteristics over the operating range [20] parameter description cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av unit -20 -25 min max min max read cycle t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha output hold from address change 3 3 ns t ace [21] ce low to data valid 20 25 ns t doe oe low to data valid 12 13 ns t lzoe [22, 23, 24] oe low to low z 3 3 ns t hzoe [22, 23, 24] oe high to high z 12 15 ns t lzce [22, 23, 24] ce low to low z 3 3 ns t hzce [22, 23, 24] ce high to high z 12 15 ns t pu [24] ce low to power up 0 0 ns t pd [24] ce high to power down 20 25 ns t abe [21] byte enable access time 20 25 ns write cycle t wc write cycle time 20 25 ns t sce [21] ce low to write end 15 20 ns t aw address valid to write end 15 20 ns t ha address hold from write end 0 0 ns t sa [21] address setup to write start 0 0 ns notes 20. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 21. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 22. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 23. test conditions used are load 3. 24. this parameter is guaranteed but not tested. for information on port to port delay through ram cells from writing port to re ading port, refer to figure 12 . [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 10 of 20 data retention mode the cy7c024av/024bv/025av/026av and cy7c0241av/0251av/036av are designed for battery backup. data retention voltage and s upply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high du ring data retention, within v cc to v cc ? 0.2v. 2. ce must be kept between v cc ? 0.2v and 70 percent of v cc during the power up and power down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (3.0v). notes 25. for information on port to port delay through ram cells from writing port to reading port, refer to figure 12 . 26. test conditions used are load 2. 27. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 28. ce = v cc , v in = gnd to v cc , t a = 25 ? c. this parameter is guaranteed but not tested. t pwe write pulse width 15 20 ns t sd data setup to write end 15 15 ns t hd data hold from write end 0 0 ns t hzwe [23, 24] r/w low to high z 12 15 ns t lzwe [23, 24] r/w high to low z 3 0 ns t wdd [25] write pulse to data delay 45 50 ns t ddd [25] write data valid to read data valid 30 35 ns busy timing [26] t bla busy low from address match 20 20 ns t bha busy high from address mismatch 20 20 ns t blc busy low from ce low 20 20 ns t bhc busy high from ce high 17 17 ns t ps port setup for priority 5 5 ns t wb r/w high after busy (slave) 0 0 ns t wh r/w high after busy high (slave) 15 17 ns t bdd [27] busy high to data valid 20 25 ns interrupt timing [26] t ins int set time 20 20 ns t inr int reset time 20 20 ns semaphore timing t sop sem flag update pulse (oe or sem )1012ns t swrd sem flag write to read time 5 5 ns t sps sem flag contention window 5 5 ns t saa sem address access time 20 25 ns switching characteristics over the operating range (continued) [20] parameter description cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av unit -20 -25 min max min max timing parameter test conditions [28] max unit icc dr1 at vcc dr = 2v 50 ? a data retention mode 3.0v 3.0v v cc ? ? 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 11 of 20 switching waveforms notes 29. r/w is high for read cycles. 30. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 31. oe = v il . 32. address valid prior to or coincident with ce transition low. 33. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha figure 5. read cycle no. 1 (either port address access) [29, 30, 31] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current figure 6. read cycle no. 2 (either port ce /oe access) [29, 32, 33] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce figure 7. read cycle no. 3 (either port) [29, 31, 32, 33] [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 12 of 20 notes 34. r/w or ce must be high during all address transitions. 35. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 36. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 37. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to enable the io drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 38. to access ram, ce = v il , sem = v ih . 39. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 40. transition is measured ? 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and not 100 percent tested. 41. during this period, the io pins are in the ou tput state, and input signals must not be applied. 42. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe figure 8. write cycle no. 1: r/w controlled timing [34, 35, 36, 37] [40] [40] [37] [38, 39] note 41 note 41 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa figure 9. write cycle no. 2: ce controlled timing [34, 35, 36, 42] [38, 39] [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 13 of 20 notes 43. ce = high for the duration of the above timing (both write and read cycle). 44. io 0r = io 0l = low (request semaphore); ce r = ce l = high. 45. semaphores are reset (available to both ports) at cycle start. 46. if t sps is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable . switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w io 0 sem a 0 ?a 2 figure 10. semaphore read after write timing, either side [43] match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r figure 11. timing diagram of semaphore contention [44, 45, 46] [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 14 of 20 note 47. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l figure 12. timing diagram of read with busy (m/s =high) [47] t pwe r/w busy t wb t wh figure 13. write timing with busy input (m/s =low) [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 15 of 20 note 48. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy is asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r figure 14. busy timing diagram no.1 (ce arbitration) [48] ce l valid first address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: figure 15. busy timing diagram no.2 (address arbitration) [48] left address valid first: [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 16 of 20 notes 49. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 50. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write 1fff (or 1/3fff) t wc right side clears int r : t ha read 7fff t rc t inr write 1ffe (or 1/3ffe) t wc right side sets int l : left side sets int r : left side clears int l : read 7ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (or 1/3fff) or 1/3ffe) [49] [50] [50] [50] [49] [50] figure 16. interrupt timing diagram [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 17 of 20 ordering information ordering code definitions 4k x16 3.3v asynchronous dual-port sram speed (ns) ordering code package diagram package type operating range 15 cy7c024bv-15axi 51-85048 100-pin pb-free thin quad flat pack industrial 20 cy7c024av-20axc 51-85048 100-pin pb-free thin quad flat pack commercial cy7c024av-20axi 51-85048 100-pin pb-free thin quad flat pack industrial 25 cy7c024av-25axc 51-85048 100-pin pb-free thin quad flat pack commercial cy7c024av-25axi 51-85048 100-pin pb-free thin quad flat pack industrial 8k x16 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c025av-20axc 51-85048 100-pin pb-free thin quad flat pack commercial 25 cy7c025av-25axc 51-85048 100-pin pb-free thin quad flat pack commercial cy7c025av-25axi 51-85048 100-pin pb-free thin quad flat pack industrial 16k x16 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c026av-20axc 51-85048 100-pin pb-free thin quad flat pack commercial 25 cy7c026av-25ac 51-85048 100-pin thin quad flat pack commercial cy7c026av-25axc 51-85048 100-pin pb-free thin quad flat pack cy7c026av-25ai 51-85048 100-pin th in quad flat pack industrial cy7c026av-25axi 51-85048 100-pin pb-free thin quad flat pack temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: a = 100-pin tqfp speed grade: xx = 15 ns or 20 ns or 25 ns xx = av/bv - 3.3 v depth: x = 4 or 5 or 6 4 = 4k; 5 = 8k; 6 = 16k 02 = width: 16 7c = dual port sram cy = cypress device 7c cy 02 x - xx x x x xx [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 18 of 20 package diagram figure 17. 100-pin pb-free thin plastic quad flat pack (tqfp) a100 51-85048 *e [+] feedback
cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av document #: 38-06052 rev. *m page 19 of 20 document history page document title: cy7c024av/024bv/025av/026av, cy7c0241av/0 251av/036av 3.3v 4k/8k/16k x 16/18 dual-port static ram document number: 38-06052 rev. ecn no. orig. of change submission date description of change ** 110204 szv 11/11/01 change from spec number: 38-00838 to 38-06052 *a 122302 rbi 12/27/02 power up requirements added to maximum ratings information *b 128958 jfu 9/03/03 added cy7c025av-25ai to ordering information *c 237622 ydt see ecn removed cross information from features section *d 241968 wwz see ecn added cy7c024av-25ai to ordering information *e 276451 spn see ecn corrected x18 for 026av to x16 *f 279452 ruy see ecn added pb-free packaging information corrected pin a113l to a13l on cy7c026av pin list added minimum v il of 0.3v and note 16 *g 373580 ruy see ecn corrected cy7c024ac-25axc to cy7c024av-25axc in ordering information *h 380476 pcx see ecn added to part ordering information: cy7c024av-15ai, cy7c024av-15axi, cy7c024av-20ai, cy7c024av-20axi, cy7c025av-20axi, cy7c026av-20axi *i 2543577 nxr/aesa 07/25/08 updated note number 33 on page 12 from ?r/w must be high during all address transitions? to ?r/w or ce must be high during all address transitions? *j 2623540 vkn/pyrs 12/17/08 added cy7c024bv part *k 2896038 rame 03/19/10 removed inactive parts from ordering information table updated package diagram *l 3110406 admu 12/14/2010 added ordering code definitions . *m 3210221 admu 03/30/2011 updated pa ckage diagram from *d to *e part cy7c025av-25ac from ordering information table. [+] feedback
document #: 38-06052 rev. *m revised march 30, 2011 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c024av/024bv/025av/026av cy7c0241av/0251av/036av ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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